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Q No.1 of 10

If following memory configurations:

ADDRESS	VALUE
1	5
5	7
7	11
10	3

Register R: 5

Then

If the instruction ADD A TO B gives 16, then the addressing mode for A, B will be

Option 1

register(direct) and auto-increment direct respectively

Option 2

register(direct) and auto-increment indirect respectively

Option 3

register(indirect) and auto-increment indirect respectively

Option 4

register(indirect) and auto-increment direct respectively

Q No.2 of 10

A programming language is to be designed to run on a machine that does not have a big memory.

Option 1

prefer an interpreter to a compiler

Option 2

not support recursion

Option 3

prefer a two-pass compiler to an one-pass compiler

Option 4

All of these

Q No.3 of 10

__________is not assembler directive?

Option 1

BYTE

Option 2

START

Option 3

LOAD

Option 4

END

Q No.4 of 10

____________ is incorrect about loader?

Option 1

Linkage editors perform linking after loading

Option 2

Loader brings object program into memory for execution.

Option 3

Dynamic linking schemes delay linking until execution time.

Option 4

All of these

Q No.5 of 10

In a two-pass assembler the pseudo-code EQU is to be evaluated during___________

Option 1

pass 2

Option 2

pass 1

Option 3

not evaluated by the assembler

Option 4

none of the above

Q No.6 of 10

About the assembler the following remarks is/are true?

Option 1

It translates mnemonic instruction into machine code.

Option 2

The instruction formats, addressing modes, etc are of direct concern in assembler design.

Option 3

All of these

Option 4

None of these

Q No.7 of 10

Following statement about the macro-processors is/are incorrect.

Option 1

Macro invocation includes the name, of the macro being called and the arguments to be used.

Option 2

The general features such as macro expansion. Use of keyword parameters are machine dependent.

Option 3

All of these

Option 4

None of these

Q No.8 of 10

The H/W signal given is__________, when exceptional situation occurs outside the CPU.

Option 1

wait

Option 2

hold

Option 3

interrupt

Option 4

reset

Q No.9 of 10

Efficient use of addressing modes is/are________.

Option 1

reduces the member of instructions

Option 2

speeds up execution

Option 3

all of these

Option 4

none of these

Q No.10 of 10

___________ addressing modes support Indexing?

Option 1

Memory indirect

Option 2

Immediate

Option 3

Relative

Option 4

None of these